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1 ? fn8200.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x9440 mixed signal with spi interface dual digitally controlled potentiometer (xdcp?) & voltage comparator features ? two digitally controlled potentiometers and two voltage comparators in one package ? spi serial interface ? register oriented format ?direct read/write wiper position ?store as many as four positions per pot ? fast response comparator ? enable, latch, or shutdown comparator outputs through the acr ? auto-recall of wcr and acr data from r0 ? hardware write protection, wp ? separate analog and digital/system supplies ? direct write cell ?endurance?100,000 data changes per bit per register ?register data retention?100 years ? 16-bytes of eeprom memory ? power saving feature and low noise ? two 10k ? or two 2.5k ? potentiometers ? resolution: 64 taps each pot ? 24-lead tssop and 24-lead soic packages description the x9440 integrates two non volatile digitally con- trolled potentiometers (xdcp) and two voltage com- parators on a cmos mo nolithic microcircuit. the x9440 contains two re sistor arrays, each com- posed of 63 resistive elements. between each ele- ment and at either end are tap points accessible to the wiper elements. the position of the wiper element on the array is controlled by the user through the spi serial bus interface. each potentiometer has an associated voltage com- parator. the comparator compares the external input voltage v ni with the wiper voltage v w and sets the out- put voltage level to a logic high or low. each resistor array and comparator has associated with it a wiper counter register (wcr), analog control register (acr), and eight 6 bit data registers that can be directly written and read by the user. the contents of the wiper counter register controls the position of the wiper on the resistor array. the contents of the analog control register cont rols the comparator and its output. the potentiometer is programmed with a spi serial interface. block diagram v out (0,1) (r 0 -r 3 ) 0,1 interface and control circuitry sck s0 si a1 cs hold v h (0,1) v l (0,1) wp v w (0,1) v ni (0,1) + ? wcr 0,1 (r 0 -r 3 ) 0,1 acr 0,1 a0 data sheet march 28, 2005
2 fn8200.0 march 28, 2005 pin descriptions host interface pins serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9440. chip select (cs ) when cs is high, the x9440 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9440, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume com- munication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 - a 1 ) the address inputs are used to set the least significant 2 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9440. a maximum of 4 devices may share the same spi serial bus. potentiometer pins v h (v h0 -v h3 ), v l (v l0 -v l3 ) the v h and v l inputs are equivalent to the terminal con- nections on either end of a mechanical potentiometer. v w (v w0 -v w1 ) the wiper output v w is equivalent to the wiper output of a mechanical potentiometer and is connected to the inverting input of the voltage comparator. comparator and device pins voltage input v ni0 , v ni1 v ni0 and v ni1 are the input voltages to the plus (non- inverting) inputs of the two comparators. buffered voltage outputs v out0 , v out1 v out0 and v out1 are the buffered voltage comparator outputs controlled by bits in the volatile analog control register. hardware write protect input wp the wp pin when low prevents non volatile writes to the wiper counter and analog control registers. analog supplies v+, v- the analog supplies v+, v- are the supply voltages for the xdcp analog section and the voltage comparators. system supply v cc and ground v ss the system supply, v cc and its reference v ss is used to bias the interface and control circuits. x9440
3 fn8200.0 march 28, 2005 pin configuration pin names principles of operation the x9440 is a highly integrated microcircuit incorpo- rating two resistor arrays, two voltage comparators and their associated registers and counters; and the serial interface logic providing direct communication between the host and the digitally-controlled potenti- ometers and voltage comparators. serial interface the x9440 supports the spi interface hardware con- ventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outpu ts. this can help to reduce system pin count. array description the x9440 is comprised of two resistor arrays and two voltage comparators. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h and v l inputs). at both ends of each arra y and between each resistor segment is a cmos switch connected to the wiper (v w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a volatile wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written dire ctly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. voltage comparator the comparator compares the wiper voltage v w with the external input voltage v ni . the comparator and its logic level output are controlled by the shutdown, latch, and enable bits of the analog control register (acr). enable connects the comparator output to the v out pin, latch memorizes th e output logic state, and shutdown removes the analog section supply voltages to save power. the analog control register (acr) is programmed using the spi serial interface. the acr may be written dire ctly, or it can be changed by transferring the contents of one of four associated data registers into the acr. these data registers and the acr may be read and written by the host system. symbol description sck serial clock s1, so serial data a0-a1 device address v h0 -v h1 , v l0 -v l1 potentiometers (terminal equivalent) v w0 ?v w1 potentiometers (wiper equivalent) v ni0 , v ni1 comparator input voltages v out0, v out1 buffered comparator outputs wp hardware write protection v+,v- analog and voltage comparator supplies v cc system supply voltage v ss system ground nc no connection v cc v l0 v h0 wp si a1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v+ v out0 v ni0 nc a0 so hold sck nc v ni1 soic x9440 v ss v w0 14 13 11 12 cs v l1 v h1 v w1 v out1 v- 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 tssop x9440 14 13 11 12 si a1 v l1 v h1 v w1 v ss nc v- v+ v out1 v out0 sck hold v ni1 v ni0 s0 a0 v cc nc v l0 v h0 v w0 wp cs x9440
4 fn8200.0 march 28, 2005 registers both digitally-controlled potentiometers and voltage com- parators share the serial interface and share a common architecture. each potentiometer and voltage comparator is associated with wiper counter and analog control reg- isters and eight data registers. a detailed discussion of the register organization and array operation follows. wiper counter (wcr) and analog control registers (acr) the x9440 contains two wiper counter registers: one for each xdcp potentiometer and two analog control registers, and one for each of the two voltage com- parators. the wiper counter register is equivalent to a serial-in, parallel-out counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wiper counter register and analog control register can be altered in four ways: it may be written directly by the host via the write wcr instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers (dr) via the xfr data register instruc- tion (parallel load); it can be modified one step at a time by the increment/ decrement instruction (wcr only). finally, it is loaded with the contents of its data register zero (r0) upon power-up. the wiper counter and analog control register are vol- atile registers; that is, thei r contents are lost when the x9440 is powered-down. although the registers are automatically loaded with the value in r0 upon power- up, it should be noted this may be different from the value present at power-down. programming the acr is similar to the wcr. how- ever, the 6 bits in the wcr positions the wiper in the resistor array while 3 bits in the acr control the com- parator and its output. data registers (dr) each potentiometer and each voltage comparator has four non volatile data registers (dr). these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr or acr. it should be noted all operations changing data in one of these registers is a non vola- tile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer or comparator, these reg- isters can be used as regular memory locations that could store system parameter s or user preference data. figure 1. detailed pote ntiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn v h v l v w 8 6 c o u n t e r d e c o d e if wc = 00[h] v w = v l if wc = 3f[h] v w = v h wiper (one of two arrays) (wcr) x9440
5 fn8200.0 march 28, 2005 register bit descriptions wiper counter register (wcr) wp0-wp5 identify wiper position. analog control register (acr) shutdown ?1? indicates power is connected to the voltage comparator. ?0? indicates power is not connected to the voltage comparator. enable ?1? indicates the output buffer of the voltage comparator is enabled. ?0? indicates the output buffer of the voltage comparator is disabled. latch ?1? indicates the output of the voltage comparator is memorized or latched. ?0? indicates the output of the voltage comparator is not latched. userbits ?available for user applications data registers (dr, r 0 -r 3 ) {refer to memory map, figure 9} instructions and programming identification (id) byte the first byte sent to the x9440 from the host, follow- ing a cs going high to low, is called the identifica- tion byte. the most significa nt four bits of the slave address are a device type identifier, for the x9440 this is fixed as 0101[b] (refer to figure 2). the two least significant bits in the id byte select one of four devices on the bus. the physical device address is defined by the state of the a 0 -a 1 input pins. the x9440 compares the serial data stream with the address input state; a su ccessful compare of both address bits is required for the x9440 to successfully continue the command sequence. the a 0 -a 1 inputs can be actively driven by cm os input signals or tied to v cc or v ss . the remaining two bits in the slave byte must be set to 0. figure 2. identification byte format instruction byte the byte following the address contains the instruction and register pointer information. the four most signifi- cant bits are the instruction. the next four bits point to one of the two pots or two voltage comparators and when applicable they point to one of four associated registers. the format is shown below in figure 3. figure 3. instruction byte format the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four data registers t hat is to be acted upon when a register oriented instruction is issued. the last two bits (p 1 and p 0 ) selects which one of the four potenti- ometers is to be affected by the instruction. the four high order bits define the instruction. the next two bits (r 1 and r 0 ) select one of the four data registers that is to be acted upon when a register oriented instruc- tion is issued. the last two bits (p 1 and p 0 ) select which one of the two potentiometers or which one of the two voltage comparators is to be affected by the instruction. 0 0 wp5 wp4 wp3 wp2 wp1 wp0 (volatile) (lsb) 00 user- bit5 user- bit4 user- bit3 latch enable shut- down (volatile) (lsb) wiper position or analog control data or user data (nonvolatile) 1 00 0 0 a1 a0 device type identifier device address 1 i1 i2 i3 i0 r1 r0 p1 p0 pot select register select instructions x9440
6 fn8200.0 march 28, 2005 four of the ten instructions end with the transmission of the instruction byte. th e basic sequence is illus- trated in figure 4. these two-byte instructions exchange data between the wiper counter register or analog control register and on e of the data registers. a transfer from a data register to a wiper counter register or analog control register is essentially a write to a static ram. the response of the wiper to this action will be delayed t wrl . a transfer from the wiper counter register current wiper position to a data register is a write to non volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the two potentiometers or one of the two voltage comparators and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the potentiometers and voltage com- parators and one of their associated registers. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9440; ei ther between the host and one of the data registers or directly between the host and the wiper counter and analog control registers. these instructions are: re ad wiper counter register or analog control register, read the current wiper position of the selected pot or the comparator control bits, write wiper counter register or analog control register, i.e. change current wiper position of the selected pot or control the voltage comparator; read data register, read the contents of the selected non volatile register; write data register, write a new value to the selected data register. the bit structures of the instructions are shown in figure 9. the sequences of the three byte operations are shown in figure 5 and figure 6. the bit structures of the instructions and the descrip- tion of the instructions are shown in figure 10. figure 4. two-byte command sequence figure 5. three-byte command sequence (write) 010100a1a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si cs 0 101 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si 0 0 d5 d4 d3 d2 d1 d0 cs 00 x9440
7 fn8200.0 march 28, 2005 figure 6. three-byte command sequence (read) figure 7. increment/decrement command sequence increment/decrement the final command is incremen t/decrement. it is differ- ent from the other comm ands, because it?s length is indeterminate. once the co mmand is issued, the mas- ter can clock the selected wiper up and/or down in one resistor segment steps; ther eby, providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the se lected wiper will move one resistor segment towards the v h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l terminal. a detailed illust ration of the sequence and tim- ing for this operation are shown in figure 7 and 8. write in process the contents of the data re gisters are saved to nonvol- atile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write opera- tion can be monitored by a write in process bit (wip). the wip bit is read with a read status command. figure 8. increment/decrement timing limits 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si cs 00 s0 0 0 d5 d4 d3 d2 d1 d0 don?t care 010100a1a0 i3 i2 i1 i0 0 p1 p0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs sck si v w inc/dec cmd issued voltage out t wrid x9440
8 fn8200.0 march 28, 2005 figure 9. memory map figure 10. instruction set read wiper counter register (wcr) or analog control register (acr) read the contents of the wiper counter register or analog control register pointed to by p 1 - p 0 . p1 p0: 00 - wcr0, 01 - wcr1 p1 p0: 10 - acr0, 11 - acr1 write wiper counter register (wcr) or analog control register (acr) write new value to the wiper counter register or analog control register pointed to by p 1 - p 0 . p1 p0: 00 - wcr0, 01 - wcr1 p1 p0: 10 - acr0, 11 - acr1 read data register (dr) read the contents of the register pointed to by p 1 - p 0 and r 1 - r 0 . r1 r0: 00 - r0, 10 - r1 01 - r2, 11 - r3 write data register (dr) write new value to the register pointed to by p 1 - p 0 and r 1 - r 0 . wcro wcr1 acr0 acr1 r0 r0 r0 r0 r1 r1 r1 r1 r2 r2 r2 r2 r3 r3 r3 r3 cs falling edge device type identifier device addresses instruction opcode wcr/acr addresses register data (sent by slave on sda) cs rising edge 010100 a 1 a 0 100100 p 1 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode wcr/acr addresses register data (sent by master on sda) cs rising edge 010100 a 1 a 0 101000 p 1 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode wcr/acr/dr addresses register data (sent by master on sda) cs rising edge 010100 a 1 a 0 1011 r 1 r 0 p 1 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode wcr/acr/dr addresses register data (sent by master on sda) cs falling edge high-voltage write cycle 010100 a 1 a 0 1100 r 1 r 0 p 1 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 x9440
9 fn8200.0 march 28, 2005 transfer data register to wiper counter register or analog control register transfer the contents of the register pointed to by r 1 - r 0 to the wcr or acr pointed to by p 1 - p 0 . transfer wiper counter or analog control register to data register transfer the contents of the wcr or acr pointed to by p 1 - p 0 to the register pointed to by r 1 - r 0 . global transfer data register to wiper counter or analog control register transfer the contents of all four data registers pointed to by r 1 - r 0 to their respective wcr or acr. global transfer wiper counter or analog control register to data register transfer the contents of all wcrs and acrs to their respective data registers pointed to by r 1 - r 0 . increment/decrement wiper counter register enable increment/decrement of the wcr pointed to by p 1 - p 0 . p1 p0: 00 or 01 only. i/d: increment/decrement, 1/0 read status cs falling edge device type identifier device addresses instruction opcode wcr/acr/dr addresses cs rising edge 010100 a 1 a 0 1101 r 1 r 0 p 1 p 0 cs falling edge device type identifier device addresses instruction opcode wcr/acr/dr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1110 r 1 r 0 p 1 p 0 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100 a 1 a 0 0001 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1000 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on sda) cs rising edge 010100 a 1 a 0 001000 p 1 p 0 i/ d i/ d .... i/ d i/ d cs falling edge device type identifier device addresses instruction opcode wiper addresses data byte (sent by x9440 on so) cs rising edge 010100 a 1 a 0 010100010000000 w i p x9440
10 fn8200.0 march 28, 2005 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on sck, scl or any address input with respect to v ss .................................. -1v to +7v voltage on v+ (referenced to v ss ) ........................+7v voltage on v- (referenced to v ss ) ..........................-7v (v+) - (v-) .............................................................. 12v any v h .....................................................................v+ any v l ......................................................................v- lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. analog characteristics (over recommended operating condi tions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expec ted voltage as determined by wiper positi on when used as a potentiometer. (2) relative linearity is utilized to deter mine the actual change in voltage between two successive tap posit ions when used as a potentiom- eter. it is a measure of the error in step size. (3) mi = rtot/63 or (v h - v l )/63, single pot (4) individual array resolutions. recommended operating conditions temperature min. max. commercial 0 c +70c industrial -40 c+85 c military -55c +125c device supply voltage (v cc ) limits x9440 5v 10% x9440-2.7 2.7v to 5.5v symbol parameter limits test conditions min. typ. max. unit r total end to end resistance ?20 +20 % power rating 50 mw 25 c, each pot i w wiper current ?3 +3 ma r w wiper resistance 40 100 ? v cc = 5v, wiper current = 3ma 100 250 ? v cc = 2.7-5v, wiper current = 3ma vv+ voltage on v+ pin x9440 +4.5 +5.5 v x9440-2.7 +2.7 +5.5 vv- voltage on v- pin x9440 -5.5 -4.5 v x9440-2.7 -5.5 -2.7 v term voltage on any v h or v l pin v- v+ v noise -120 dbv ref: 1khz resolution (4) 1.6 % absolute linearity (1) -1 +1 mi (3) v w(n)(actual) - v w(n)(expected) relative linearity (2) -0.2 +0.2 mi (3) v w(n + 1 - [v w(n) + mi ] temperature coefficient of r total 300 ppm/ c x9440
11 fn8200.0 march 28, 2005 comparator electrical characteristics (over the recommended operating cond itions unless otherwise specified.) notes: (1) 100mv step with 100mv overdrive, zl = 10k ? || 15pf, 10-90% risetime (2) time from leading edge of enable bit to valid v out . symbol parameter limits unit test conditions min. typ. max. v os input offset voltage -1 -5 1 5 mv mv v+/v- = 3v v+/v- = 5v i b input current 10 pa v ir input voltage range v- v+ v t r response time 200 ns note 1 i o output current -1 1 ma a v voltage gain 300 v/mv psrr power supply rejection ratio 60 db v or output voltage range v ss v cc v t c v os input offset voltage drift 6 v/c i s supply current (v+ to v-) 1.2 .5 ma ma v+/v- = 5v v+/v- = 3v t on comparator enable time 1 s note 2 v ol output low voltage 0.4 v i o = 1ma v oh output high voltage v cc -0.8 v i o = 1ma x9440
12 fn8200.0 march 28, 2005 d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified.) endurance and data retention capacitance power-up sequence a.c. test conditions note: (1) applicable to recall and power consumption applica- tions equivalent a.c. load circuit symbol parameter limits test conditions min. typ. max. unit i cc1 v cc supply current (active) 400 a f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (nonvolatile write) 1maf sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 1 a sck = si = v ss , addr. = v ss i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage -0.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. unit test conditions c i/o output capacitance (so) 8 pf v out = 0v c in input capacitance (a0, a1, si, and sck) 6 pf v in = 0v c l , c h , c w potentiometer capacitance 10/10/25 pf power-up sequence (1) : (1) v cc (2) v+ and v- {v+ v cc at all times} power-down sequence: no limitation i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 ? 100pf sda output 2.7v 100pf x9440
13 fn8200.0 march 28, 2005 ac timing high-voltage wr ite cycle timing xdcp timing symbol parameter min. max. unit f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 450 s x9440
14 fn8200.0 march 28, 2005 symbol table timing diagrams input timing output timing waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... x9440
15 fn8200.0 march 28, 2005 hold timing xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) write protect and device address pins timing ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo ... cs sck si msb lsb vwx t wrl ... so high impedance ... cs sck so si addr t wrid high impedance vwx ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction) x9440
16 fn8200.0 march 28, 2005 basic applications +5v v h v+ scl sda v out ? + v? v l v ss scl sda 9440 v ref1 (+5v) v transducer (v t ) v w v out programmable window detector with memory scl + ? sda + ? +5v ?5v 9440 v w0 v w1 v out0 v out1 v out0 v s v ll v ul (v w1 )(v w0 ) v t > v w , v out = high v t < v w , v out = low + ? v out0 = l v out1 = l v out0 = h v out1 = h v out0 = l v out1 = h for the signal voltage v s > the upper limit v ul , (v out0 = h) ? (v out1 = h) v s < the lower limit v ll , (v out0 = l) ? (v out1 = l) for the window v ll v s v ul , (v out0 = l) ? (v out1 = h) v s + ? v cc v ni (+5v) (-5v) v ref2 (?5v) programmable level detector with memory (typical bias conditions) x9440
17 fn8200.0 march 28, 2005 basic application (continued) programmable oscillator with memory programmable schmitt trigger with memory +5v v h v+ scl sda ? + v? v w v out frequency r, c v l +5v r 2 r 1 r 3 r c duty cycle r 1 , r 2 , r 3 v h v+ ? + v? v out v l r 2 r 1 r v s v ll v ul v out v ll r 1 r 2 + r 2 -------------------- - v w r 1 r 2 ------ - v out max () ? = v ul r 1 r 2 + r 2 -------------------- - v w r 1 r 2 ------ - v out min () ? = v r v w v s 9440 9440 x9440
18 fn8200.0 march 28, 2005 basic application (continued) programmable level detector (alternate technique) programmable time delay with memory ? + v r v out + + r 2 { { r 1 v s v out high for v s ? r 1 r 2 ------ - v r < = v out low for v s ? r 1 r 2 ------ - v r > = r 1 r 2 +r pot = v out v s -r 1 r 2 v r v h ? + v l v w v out v ni v out dt +5v v s r c ? trc ln 5v 5v v w ? ---------------------- - ?? ?? = t t t +5v +5v +5v v s v ni v out v w v ss= v cc x9440
19 fn8200.0 march 28, 2005 packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 24-lead plastic small outline gull wing package type s note: all dimensions in inches (in pare ntheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 24 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0 - 8 x 45 x9440
20 fn8200.0 march 28, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 0 - 8 x9440
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8200.0 march 28, 2005 ordering information device v cc limits blank = 5v 10% -2.7 = 2.7 to 5.5v temperature range blank = commercial = 0c to +70c i = industrial = -40c to +85c package p24 = 24-lead plastic dip s24 = 24-lead soic v24 = 24-lead tssop potentiometer organization pot 0 pot 1 w = 10k ? 10k ? y = 2.5k ? 2.5k ? x9440 p t v y x9440

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